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PMC.P6(3) Library Functions Manual PMC.P6(3)

pmc.p6 — measurement events for Intel Pentium Pro, P-II, P-III family CPUs

library “libpmc”

#include <pmc.h>

Intel P6 PMCs are present in Intel Pentium Pro, Pentium II, Celeron, Pentium III and Pentium M processors.

They are documented in Volume 3: System Programming Guide, IA-32 Intel(R) Architecture Software Developer's Manual, Order Number 245472-012, Intel Corporation, 2003.

Some of these events are affected by processor errata described in Intel(R) Pentium(R) III Processor Specification Update, Document Number: 244453-054, Intel Corporation, April 2005.

These CPUs have two counters, each 40 bits wide. Some events may only be used on specific counters and some events are defined only on specific processor models. These PMCs support the following capabilities:

PMC_CAP_CASCADE No
PMC_CAP_EDGE Yes
PMC_CAP_INTERRUPT Yes
PMC_CAP_INVERT Yes
PMC_CAP_READ Yes
PMC_CAP_PRECISE No
PMC_CAP_SYSTEM Yes
PMC_CAP_TAGGING No
PMC_CAP_THRESHOLD Yes
PMC_CAP_USER Yes
PMC_CAP_WRITE Yes

Event specifiers for Intel P6 PMCs can have the following common qualifiers:

value
Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to value.
Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true.
Invert the sense of comparison when the “cmask” qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the “cmask” qualifier.
Configure the PMC to count events happening at processor privilege level 0.
value
This qualifier is used to further qualify the event selected (see below).
Configure the PMC to count events occurring at privilege levels 1, 2 or 3.

If neither of the “os” or “usr” qualifiers are specified, the default is to enable both.

The event specifiers supported by Intel P6 PMCs are:

(Event E6H) Count the number of times a static branch prediction was made by the branch decoder because the BTB did not have a prediction.
(Event 8AH, Pentium M) Count the number of branch instructions executed that where mispredicted at the Front End (BAC).
(Event E4H) Count the number of bogus branches.
(Event 92H, Pentium M) Count the number of call instructions executed.
(Event 93H, Pentium M) Count the number of call instructions executed that were mispredicted.
(Event 8BH, Pentium M) Count the number of conditional branch instructions executed.
(Event 8CH, Pentium M) Count the number of conditional branch instructions executed that were mispredicted.
(Event 94H, Pentium M) Count the number of indirect call instructions executed.
(Event 8DH, Pentium M) Count the number of indirect branch instructions executed.
(Event 8EH, Pentium M) Count the number of indirect branch instructions executed that were mispredicted.
(Event E0H) Count the number of branch instructions decoded.
(Event 88H, Pentium M) Count the number of branch instructions executed but necessarily retired.
(Event C4H) Count the number of branch instructions retired.
(Event C5H) Count the number of mispredicted branch instructions retired.
(Event C9H) Count the number of taken mispredicted branches retired.
(Event 89H, Pentium M) Count the number of branch instructions executed that were mispredicted at execution.
(Event 91H, Pentium M) Count the number of return instructions executed that were mispredicted at the Front End (BAC).
(Event 8FH, Pentium M) Count the number of return instructions executed.
(Event 90H, Pentium M) Count the number of return instructions executed that were mispredicted at execution.
(Event C9H) Count the number of taken branches retired.
(Event E2H) Count the number of branches for which the BTB did not produce a prediction.
(Event 61H) Count the number of bus clock cycles during which this processor is driving the BNR# pin.
(Event 64H) Count the number of bus clock cycles during which this processor is receiving data.
[,umask=qualifier]
(Event 62H) Count the number of clocks during which DRDY# is asserted. An additional qualifier may be specified, and comprises one of the following keywords:

Count transactions generated by any agent on the bus.
Count transactions generated by this processor.

The default is to count operations generated by this processor.

(Event 7AH) Count the number of bus clock cycles during which this processor is driving the HIT# pin.
(Event 7BH) Count the number of bus clock cycles during which this processor is driving the HITM# pin.
[,umask=qualifier]
(Event 63H) Count the number of clocks during with LOCK# is asserted on the external system bus. An additional qualifier may be specified and comprises one of the following keywords:

Count transactions generated by any agent on the bus.
Count transactions generated by this processor.

The default is to count operations generated by this processor.

(Event 60H) Count the number of bus requests outstanding in any given cycle.
(Event 7EH) Count the number of clock cycles during which the bus is snoop stalled.
[,umask=qualifier]
(Event 70H) Count the number of completed bus transactions of any kind. An additional qualifier may be specified and comprises one of the following keywords:

Count transactions generated by any agent on the bus.
Count transactions generated by this processor.

The default is to count operations generated by this processor.

[,umask=qualifier]
(Event 65H) Count the number of burst read transactions. An additional qualifier may be specified and comprises one of the following keywords:

Count transactions generated by any agent on the bus.
Count transactions generated by this processor.

The default is to count operations generated by this processor.

[,umask=qualifier]
(Event 6EH) Count the number of completed burst transactions. An additional qualifier may be specified and comprises one of the following keywords:

Count transactions generated by any agent on the bus.
Count transactions generated by this processor.

The default is to count operations generated by this processor.

[,umask=qualifier]
(Event 6DH) Count the number of completed deferred transactions. An additional qualifier may be specified and comprises one of the following keywords:

Count transactions generated by any agent on the bus.
Count transactions generated by this processor.

The default is to count operations generated by this processor.

[,umask=qualifier]
(Event 68H) Count the number of completed instruction fetch transactions. An additional qualifier may be specified and comprises one of the following keywords:

Count transactions generated by any agent on the bus.
Count transactions generated by this processor.

The default is to count operations generated by this processor.

[,umask=qualifier]
(Event 69H) Count the number of completed invalidate transactions. An additional qualifier may be specified and comprises one of the following keywords:

Count transactions generated by any agent on the bus.
Count transactions generated by this processor.

The default is to count operations generated by this processor.

[,umask=qualifier]
(Event 6FH) Count the number of completed memory transactions. An additional qualifier may be specified and comprises one of the following keywords:

Count transactions generated by any agent on the bus.
Count transactions generated by this processor.

The default is to count operations generated by this processor.

[,umask=qualifier]
(Event 6AH) Count the number of completed partial write transactions. An additional qualifier may be specified and comprises one of the following keywords:

Count transactions generated by any agent on the bus.
Count transactions generated by this processor.

The default is to count operations generated by this processor.

[,umask=qualifier]
(Event 66H) Count the number of completed read-for-ownership transactions. An additional qualifier may be specified and comprises one of the following keywords:

Count transactions generated by any agent on the bus.
Count transactions generated by this processor.

The default is to count operations generated by this processor.

[,umask=qualifier]
(Event 6CH) Count the number of completed I/O transactions. An additional qualifier may be specified and comprises one of the following keywords:

Count transactions generated by any agent on the bus.
Count transactions generated by this processor.

The default is to count operations generated by this processor.

[,umask=qualifier]
(Event 6BH) Count the number of completed partial transactions. An additional qualifier may be specified and comprises one of the following keywords:

Count transactions generated by any agent on the bus.
Count transactions generated by this processor.

The default is to count operations generated by this processor.

[,umask=qualifier]
(Event 67H) Count the number of completed write-back transactions. An additional qualifier may be specified and comprises one of the following keywords:

Count transactions generated by any agent on the bus.
Count transactions generated by this processor.

The default is to count operations generated by this processor.

(Event 79H) Count the number of cycles during with the processor was not halted.

(Pentium M) Count the number of cycles during with the processor was not halted and not in a thermal trip.

(Event 14H) Count the number of cycles during which the divider is busy and cannot accept new divides. This event is only allocated on counter 0.
(Event C7H) Count the number of processor cycles for which interrupts were disabled and interrupts were pending.
(Event C6H) Count the number of processor cycles for which interrupts were disabled.
(Event 43H) Count all loads and all stores using any memory type, including internal retries. Each part of a split store is counted separately.
(Event 45H) Count the total lines allocated in the data cache unit.
(Event 46H) Count the number of M state lines allocated in the data cache unit.
(Event 47H) Count the number of M state lines evicted from the data cache unit.
(Event 48H) Count the weighted number of cycles while a data cache unit miss is outstanding, incremented by the number of outstanding cache misses at any time.
(Event 13H) Count the number of integer and floating-point divides including speculative divides. This event is only allocated on counter 1.
(Event D7H, Pentium M) Count the total number of micro-ops.
[,umask=qualifier]
(Event 58H, Pentium M) Count the number of Enhanced Intel SpeedStep transitions. An additional qualifier may be specified, and can be one of the following keywords:

Count all transitions.
Count only frequency transitions.

The default is to count all transitions.

[,umask=qualifier]
(Event DAH, Pentium M) Count the number of retired fused micro-ops. An additional qualifier may be specified, and may be one of the following keywords:

Count all fused micro-ops.
Count only load and op micro-ops.
Count only STD/STA micro-ops.

The default is to count all fused micro-ops.

(Event D9H, Pentium III) Count the number of SSE computational instructions retired. An additional qualifier may be specified, and comprises one of the following keywords:

Count packed and scalar operations.
Count scalar operations only.

The default is to count packed and scalar operations.

[,umask=qualifier]
(Event D8H, Pentium III) Count the number of SSE instructions retired. An additional qualifier may be specified, and comprises one of the following keywords:

Count packed and scalar operations.
Count scalar operations only.

The default is to count packed and scalar operations.

[,umask=qualifier]
(Event 07H, Pentium III) Count the number of SSE prefetch or weakly ordered instructions dispatched (including speculative prefetches). An additional qualifier may be specified, and comprises one of the following keywords:

Count non-temporal prefetches.
Count prefetches to L1.
Count prefetches to L2.
Count weakly ordered stores.

The default is to count non-temporal prefetches.

[,umask=qualifier]
(Event 4BH, Pentium III) Count the number of prefetch or weakly ordered instructions that miss all caches. An additional qualifier may be specified, and comprises one of the following keywords:

Count non-temporal prefetches.
Count prefetches to L1.
Count prefetches to L2.
Count weakly ordered stores.

The default is to count non-temporal prefetches.

(Event F8H, Pentium M) Count the number of downward prefetches issued.
(Event F0H, Pentium M) Count the number of upward prefetches issued.
(Event CEH, Pentium M) Count the number of retired MMX instructions.
[,umask=qualifier]
(Event D9H, Pentium M) Count the number of computational SSE instructions retired. An additional qualifier may be specified and can be one of the following keywords:

Count SSE packed-single instructions.
Count SSE scalar-single instructions.
Count SSE2 packed-double instructions.
Count SSE2 scalar-double instructions.

The default is to count SSE packed-single instructions.

[,umask=qualifier]
(Event D8H, Pentium M) Count the number of SSE instructions retired. An additional qualifier can be specified, and can be one of the following keywords:

Count SSE packed-single instructions.
Count SSE packed-single and scalar-single instructions.
Count SSE2 packed-double instructions.
Count SSE2 scalar-double instructions.

The default is to count SSE packed-single instructions.

(Event D3H, Pentium M) Count the number of sync micro-ops.
(Event 59H, Pentium M) Count the duration or occurrences of thermal trips. Use the “edge” qualifier to count occurrences of thermal trips.
(Event DBH, Pentium M) Count the number of unfusion events in the reorder buffer.
(Event C1H) Count the number of computational floating point operations retired. This event is only allocated on counter 0.
(Event 11H) Count the number of floating point exceptions handled by microcode. This event is only allocated on counter 1.
(Event 10H) Count the number of computation floating point operations executed. This event is only allocated on counter 0.
[,umask=qualifier]
(Event CCH, Pentium II, Pentium III) Count the number of transitions between MMX and floating-point instructions. An additional qualifier may be specified, and comprises one of the following keywords:

Count transitions from MMX instructions to floating-point instructions.
Count transitions from floating-point instructions to MMX instructions.

The default is to count MMX to floating-point transitions.

(Event C8H) Count the number of hardware interrupts received.
(Event 80H) Count the number of instruction fetches, both cacheable and non-cacheable.
(Event 81H) Count the number of instruction fetch misses (i.e., those that produce memory accesses).
(Event 86H) Count the number of cycles instruction fetch is stalled for any reason.
(Event 87H) Count the number of cycles the instruction length decoder is stalled.
(Event D0H) Count the number of instructions decoded.
(Event C0H) Count the number of instructions retired.
(Event 85H) Count the number of instruction TLB misses.
(Event 21H) Count the number of L2 address strobes.
(Event 22H) Count the number of cycles during which the L2 cache data bus was busy.
(Event 23H) Count the number of cycles during which the L2 cache data bus was busy transferring read data from L2 to the processor.
[,umask=qualifier]
(Event 28H) Count the number of L2 instruction fetches. An additional qualifier may be specified and comprises a list of the following keywords separated by ‘+’ characters:

Count operations affecting E (exclusive) state lines.
Count operations affecting I (invalid) state lines.
Count operations affecting M (modified) state lines.
Count operations affecting S (shared) state lines.

The default is to count operations affecting all (MESI) state lines.

[,umask=qualifier]
(Event 29H) Count the number of L2 data loads. An additional qualifier may be specified and comprises a list of the following keywords separated by ‘+’ characters:

(Pentium M) Count both hardware-prefetched lines and non-hardware-prefetched lines.
Count operations affecting E (exclusive) state lines.
(Pentium M) Count hardware-prefetched lines only.
Count operations affecting I (invalid) state lines.
Count operations affecting M (modified) state lines.
(Pentium M) Exclude hardware-prefetched lines.
Count operations affecting S (shared) state lines.

The default on processors other than Pentium M processors is to count operations affecting all (MESI) state lines. The default on Pentium M processors is to count both hardware-prefetched and non-hardware-prefetch operations on all (MESI) state lines. (Errata) This event is affected by processor errata E53.

[,umask=qualifier]
(Event 24H) Count the number of L2 lines allocated. An additional qualifier may be specified and comprises a list of the following keywords separated by ‘+’ characters:

(Pentium M) Count both hardware-prefetched lines and non-hardware-prefetched lines.
Count operations affecting E (exclusive) state lines.
(Pentium M) Count hardware-prefetched lines only.
Count operations affecting I (invalid) state lines.
Count operations affecting M (modified) state lines.
(Pentium M) Exclude hardware-prefetched lines.
Count operations affecting S (shared) state lines.

The default on processors other than Pentium M processors is to count operations affecting all (MESI) state lines. The default on Pentium M processors is to count both hardware-prefetched and non-hardware-prefetch operations on all (MESI) state lines. (Errata) This event is affected by processor errata E45.

[,umask=qualifier]
(Event 26H) Count the number of L2 lines evicted. An additional qualifier may be specified and comprises a list of the following keywords separated by ‘+’ characters:

(Pentium M) Count both hardware-prefetched lines and non-hardware-prefetched lines.
Count operations affecting E (exclusive) state lines.
(Pentium M) Count hardware-prefetched lines only.
Count operations affecting I (invalid) state lines.
Count operations affecting M (modified) state lines.
(Pentium M only) Exclude hardware-prefetched lines.
Count operations affecting S (shared) state lines.

The default on processors other than Pentium M processors is to count operations affecting all (MESI) state lines. The default on Pentium M processors is to count both hardware-prefetched and non-hardware-prefetch operations on all (MESI) state lines. (Errata) This event is affected by processor errata E45.

(Event 25H) Count the number of modified lines allocated in L2 cache.
[,umask=qualifier]
(Event 27H) Count the number of L2 M-state lines evicted.

(Pentium M) On these processors an additional qualifier may be specified and comprises a list of the following keywords separated by ‘+’ characters:

Count both hardware-prefetched lines and non-hardware-prefetched lines.
Count hardware-prefetched lines only.
Exclude hardware-prefetched lines.

The default is to count both hardware-prefetched and non-hardware-prefetch operations. (Errata) This event is affected by processor errata E53.

[,umask=qualifier]
(Event 2EH) Count the total number of L2 requests. An additional qualifier may be specified and comprises a list of the following keywords separated by ‘+’ characters:

Count operations affecting E (exclusive) state lines.
Count operations affecting I (invalid) state lines.
Count operations affecting M (modified) state lines.
Count operations affecting S (shared) state lines.

The default is to count operations affecting all (MESI) state lines.

(Event 2AH) Count the number of L2 data stores. An additional qualifier may be specified and comprises a list of the following keywords separated by ‘+’ characters:

Count operations affecting E (exclusive) state lines.
Count operations affecting I (invalid) state lines.
Count operations affecting M (modified) state lines.
Count operations affecting S (shared) state lines.

The default is to count operations affecting all (MESI) state lines.

(Event 03H) Count the number of load operations delayed due to store buffer blocks.
(Event 05H) Count the number of misaligned data memory references (crossing a 64 bit boundary).
(Event CDH, Pentium II, Pentium III) Count the number of MMX assists executed.
(Event B0H) (Celeron, Pentium II) Count the number of MMX instructions executed, except MOVQ and MOVD stores from register to memory.
(Event CEH, Pentium II) Count the number of MMX instructions retired.
[,umask=qualifier]
(Event B3H, Pentium II, Pentium III) Count the number of MMX instructions executed. An additional qualifier may be specified and comprises a list of the following keywords separated by ‘+’ characters:

Count MMX pack operation instructions.
Count MMX packed arithmetic instructions.
Count MMX packed logical instructions.
Count MMX packed multiply instructions.
Count MMX packed shift instructions.
Count MMX unpack operation instructions.

The default is to count all operations.

(Event B1H, Pentium II, Pentium III) Count the number of MMX saturating instructions executed.
(Event B2H, Pentium II, Pentium III) Count the number of MMX micro-ops executed.
(Event 12H) Count the number of integer and floating-point multiplies, including speculative multiplies. This event is only allocated on counter 1.
(Event D2H) Count the number of cycles or events for partial stalls.
(Event A2H) Count the number of cycles there was a resource related stall of any kind.
(Event D6H, Pentium II, Pentium III) Count the number of segment register rename events retired.
(Event 04H) Count the number of cycles the store buffer is draining.
[,umask=qualifier]
(Event D5H, Pentium II, Pentium III) Count the number of segment register renames. An additional qualifier may be specified, and comprises a list of the following keywords separated by ‘+’ characters:

Count renames for segment register DS.
Count renames for segment register ES.
Count renames for segment register FS.
Count renames for segment register GS.

The default is to count operations affecting all segment registers.

(Event D4H, Pentium II, Pentium III) Count the number of segment register renaming stalls. An additional qualifier may be specified, and comprises a list of the following keywords separated by ‘+’ characters:

Count stalls for segment register DS.
Count stalls for segment register ES.
Count stalls for segment register FS.
Count stalls for segment register GS.

The default is to count operations affecting all the segment registers.

(Event 06H) Count the number of segment register loads.
(Event C2H) Count the number of micro-ops retired.

The following table shows the mapping between the PMC-independent aliases supported by library “libpmc” and the underlying hardware events used.

pmc(3), pmc.atom(3), pmc.core(3), pmc.core2(3), pmc.iaf(3), pmc.k7(3), pmc.k8(3), pmc.p4(3), pmc.p5(3), pmc.soft(3), pmc.tsc(3), pmclog(3), hwpmc(4)

The pmc library first appeared in FreeBSD 6.0.

The library “libpmc” library was written by Joseph Koshy <jkoshy@FreeBSD.org>.

October 4, 2008 FreeBSD-12.0