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PMC.K8(3) Library Functions Manual PMC.K8(3)

pmc.k8 — measurement events for AMD Athlon 64 (K8 family) CPUs

library “libpmc”

#include <pmc.h>

AMD K8 PMCs are present in the AMD Athlon64 and AMD Opteron series of CPUs. They are documented in the BIOS and Kernel Developer's Guide for the AMD Athlon(tm) 64 and AMD Opteron Processors, Publication No. 26094, Advanced Micro Devices, Inc., April 2004.

AMD K8 PMCs are 48 bits wide. Each CPU contains 4 PMCs with the following capabilities:

PMC_CAP_CASCADE No
PMC_CAP_EDGE Yes
PMC_CAP_INTERRUPT Yes
PMC_CAP_INVERT Yes
PMC_CAP_READ Yes
PMC_CAP_PRECISE No
PMC_CAP_SYSTEM Yes
PMC_CAP_TAGGING No
PMC_CAP_THRESHOLD Yes
PMC_CAP_USER Yes
PMC_CAP_WRITE Yes

Event specifiers for AMD K8 PMCs can have the following optional qualifiers:

value
Configure the counter to increment only if the number of configured events measured in a cycle is greater than or equal to value.
Configure the counter to only count negated-to-asserted transitions of the conditions expressed by the other fields. In other words, the counter will increment only once whenever a given condition becomes true, irrespective of the number of clocks during which the condition remains true.
Invert the sense of comparison when the “count” qualifier is present, making the counter to increment when the number of events per cycle is less than the value specified by the “count” qualifier.
qualifier
Many event specifiers for AMD K8 PMCs need to be additionally qualified using a mask qualifier. These additional qualifiers are event-specific and are documented along with their associated event specifiers below.
Configure the PMC to count events happening at privilege level 0.
Configure the PMC to count events occurring at privilege levels 1, 2 or 3.

If neither of the “os” or “usr” qualifiers were specified, the default is to enable both.

The event specifiers supported on AMD K8 PMCs are:

(Event 76H) Count the number of clock cycles when the CPU is not in the HLT or STPCLK states.
[,mask=qualifier]
(Event 7EH) Count fill requests that missed in the L2 cache. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

Count data cache fill requests.
Count instruction cache fill requests.
Count TLB reloads.

The default is to count all types of requests.

[,mask=qualifier]
(Event 7FH) The number of lines written to and from the L2 cache. The event may be further qualified by using qualifier, which is a ‘+’ separated set of the following keywords:

Count lines written into L2 cache due to victim writebacks from the Icache or Dcache, TLB page table walks or hardware data prefetches.
Count writebacks of dirty lines from L2 to the system.
[,mask=qualifier]
(Event 7DH) Count internally generated requests to the L2 cache. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

Count cancelled requests.
Count data cache fill requests.
Count instruction cache fill requests.
Count tag snoop requests.
Count TLB reloads.

The default is to count all types of requests.

(Event 40H) Count data cache accesses including microcode scratch pad accesses.
[,mask=qualifier]
(Event 44H) Count data cache copyback operations. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

Count operations for lines in the “exclusive” state.
Count operations for lines in the “invalid” state.
Count operations for lines in the “modified” state.
Count operations for lines in the “owner” state.
Count operations for lines in the “shared” state.

The default is to count operations for lines in all the above states.

[,mask=qualifier]
(Event 4CH) Count data cache accesses by lock instructions. This event is only available on processors of revision C or later vintage. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

Count data cache accesses by lock instructions.
Count data cache misses by lock instructions.

The default is to count all accesses.

[,mask=qualifier]
(Event 4BH) Count the number of dispatched prefetch instructions. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

Count load operations.
Count non-temporal operations.
Count store operations.

The default is to count all operations.

(Event 45H) Count L1 DTLB misses that are L2 DTLB hits.
(Event 46H) Count L1 DTLB misses that are also misses in the L2 DTLB.
(Event 49H) Count microarchitectural early cancels of data cache accesses.
(Event 48H) Count microarchitectural late cancels of data cache accesses.
(Event 47H) Count misaligned data references.
(Event 41H) Count data cache misses.
[,mask=qualifier]
(Event 4AH) Count one bit ECC errors found by the scrubber. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

Count scrubber detected errors.
Count piggyback scrubber errors.

The default is to count both kinds of errors.

[,mask=qualifier]
(Event 42H) Count data cache refills from L2 cache. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

Count operations for lines in the “exclusive” state.
Count operations for lines in the “invalid” state.
Count operations for lines in the “modified” state.
Count operations for lines in the “owner” state.
Count operations for lines in the “shared” state.

The default is to count operations for lines in all the above states.

[,mask=qualifier]
(Event 43H) Count data cache refills from system memory. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

Count operations for lines in the “exclusive” state.
Count operations for lines in the “invalid” state.
Count operations for lines in the “modified” state.
Count operations for lines in the “owner” state.
Count operations for lines in the “shared” state.

The default is to count operations for lines in all the above states.

(Event 01H) Count cycles when no FPU ops were retired. This event is supported in revision B and later CPUs.
(Event 02H) Count dispatched FPU ops that use the fast flag interface. This event is supported in revision B and later CPUs.
[,mask=qualifier]
(Event 00H) Count the number of dispatched FPU ops. This event is supported in revision B and later CPUs. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

Count add pipe ops excluding junk ops.
Count junk ops in the add pipe.
Count multiply pipe ops excluding junk ops.
Count junk ops in the multiply pipe.
Count store pipe ops excluding junk ops
Count junk ops in the store pipe.

The default is to count all types of ops.

(Event D0H) Count cycles when there was nothing to dispatch (i.e., the decoder was empty).
(Event D4H) Count dispatch stalls for segment loads.
(Event D3H) Count dispatch stalls for serialization.
(Event D2H) Count dispatch stalls from branch abort to retiral.
(Event D7H) Count dispatch stalls when the FPU is full.
(Event D8H) Count dispatch stalls when the load/store unit is full.
(Event D5H) Count dispatch stalls when the reorder buffer is full.
(Event D6H) Count dispatch stalls when reservation stations are full.
(Event DAH) Count dispatch stalls when a far control transfer or a resync branch is pending.
(Event D9H) Count dispatch stalls when waiting for all to be quiet.
(Event D1H) Count all dispatch stalls.
[,mask=qualifier]
(Event DBH) Count FPU exceptions. This event is supported in revision B and later CPUs. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

Count SSE and x87 microtraps.
Count SSE reclass microfaults
Count SSE retype microfaults
Count x87 reclass microfaults.

The default is to count all types of exceptions.

(Event CDH) Count cycles when interrupts were masked (by CPU RFLAGS field IF was zero).
(Event CEH) Count cycles while interrupts were masked while pending (i.e., cycles when INTR was asserted while CPU RFLAGS field IF was zero).
(Event DCH) Count the number of breakpoints for DR0.
(Event DDH) Count the number of breakpoints for DR1.
(Event DEH) Count the number of breakpoints for DR2.
(Event DFH) Count the number of breakpoints for DR3.
(Event C2H) Count retired branches including exceptions and interrupts.
(Event C3H) Count mispredicted retired branches.
(Event C6H) Count retired far control transfers (which are always mispredicted).
[,mask=qualifier]
(Event CCH) Count retired fastpath double op instructions. This event is supported in revision B and later CPUs. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

Count instructions with the low op in position 0.
Count instructions with the low op in position 1.
Count instructions with the low op in position 2.

The default is to count all types of instructions.

[,mask=qualifier]
(Event CBH) Count retired FPU instructions. This event is supported in revision B and later CPUs. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

Count MMX and 3DNow! instructions.
Count packed SSE and SSE2 instructions.
Count scalar SSE and SSE2 instructions
Count x87 instructions.

The default is to count all types of instructions.

(Event C8H) Count retired near returns.
(Event C9H) Count mispredicted near returns.
(Event C7H) Count retired resyncs (non-control transfer branches).
(Event C4H) Count retired taken branches.
(Event C5H) Count retired taken branches that were mispredicted.
(Event CAH) Count retired taken branches that were mispredicted only due to an address miscompare.
(Event CFH) Count retired taken hardware interrupts.
(Event C1H) Count retired uops.
(Event C0H) Count retired x86 instructions including exceptions and interrupts.
(Event 80H) Count instruction cache fetches.
(Event 87H) Count cycles in stalls due to instruction fetch.
(Event 84H) Count L1 ITLB misses that are L2 ITLB hits.
(Event 85H) Count ITLB misses that miss in both L1 and L2 ITLBs.
(Event 86H) Count microarchitectural resyncs caused by snoops.
(Event 81H) Count instruction cache misses.
(Event 82H) Count instruction cache refills from L2 cache.
(Event 83H) Count instruction cache refills from system memory.
(Event 88H) Count hits to the return stack.
(Event 89H) Count overflows of the return stack.
(Event 23H) Count load/store buffer2 full events.
[,mask=qualifier]
(Event 24H) Count locked operations. For revision C and later CPUs, the following qualifiers are supported:

Count the number of cycles in the lock request/grant stage.
Count the number of cycles a lock takes to complete once it is non-speculative and is the older load/store operation.
Count the number of lock instructions executed.

The default is to count the number of lock instructions executed.

(Event 25H) Count microarchitectural late cancels of operations in the load/store unit.
(Event 21H) Count microarchitectural resyncs caused by self-modifying code.
(Event 22H) Count microarchitectural resyncs caused by snoops.
(Event 26H) Count retired CFLUSH instructions.
(Event 27H) Count retired CPUID instructions.
[,mask=qualifier]
(Event 20H) Count segment register loads. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:
Count CS register loads.
Count DS register loads.
Count ES register loads.
Count FS register loads.
Count GS register loads.
Count SS register loads.

The default is to count all types of loads.

[,mask=qualifier]
 
[,mask=qualifier]
 
[,mask=qualifier]
(Events F6H, F7H and F8H respectively) Count events on the HyperTransport(tm) buses. These events may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

Count buffer release messages sent.
Count command messages sent.
Count data messages sent.
Count nop messages sent.

The default is to count all types of messages.

[,mask=qualifier]
(Event E4H) Count memory controller bypass counter saturation events. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

Count DRAM controller interface bypass.
Count DRAM controller queue bypass.
Count memory controller high priority bypasses.
Count memory controller low priority bypasses.
(Event E2H) Count memory controller DRAM command slots missed (in MemClks).
[,mask=qualifier]
(Event E0H) Count memory controller page access events. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

Count page conflicts.
Count page hits.
Count page misses.

The default is to count all types of events.

(Event E1H) Count memory control page table overflow events.
[,mask=qualifier]
(Event E3H) Count memory control turnaround events. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

Count DIMM turnarounds.
Count read to write turnarounds.
Count write to read turnarounds.

The default is to count all types of events.

[,mask=qualifier]
(Event ECH) Count probe events. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

Count all probe hits.
Count probe hits without memory cancels.
Count probe hits with memory cancels.
Count probe misses.
[,mask=qualifier]
(Event EBH) Count sized commands issued. This event may be further qualified using qualifier, which is a ‘+’ separated set of the following keywords:

 
 
 
 
 
 
 

The default is to count all types of commands.

The following table shows the mapping between the PMC-independent aliases supported by library “libpmc” and the underlying hardware events used.

pmc(3), pmc.atom(3), pmc.core(3), pmc.core2(3), pmc.iaf(3), pmc.k7(3), pmc.p4(3), pmc.p5(3), pmc.p6(3), pmc.soft(3), pmc.tsc(3), pmclog(3), hwpmc(4)

The pmc library first appeared in FreeBSD 6.0.

The library “libpmc” library was written by Joseph Koshy <jkoshy@FreeBSD.org>.

October 4, 2008 FreeBSD-12.0