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PMC.CORE2(3) Library Functions Manual PMC.CORE2(3)

pmc.core2 — measurement events for Intel Core2 family CPUs

library “libpmc”

#include <pmc.h>

Intel Core2 CPUs contain PMCs conforming to version 2 of the Intel performance measurement architecture. These CPUs may contain up to two classes of PMCs:
Fixed-function counters that count only one hardware event per counter.
Programmable counters that may be configured to count one of a defined set of hardware events.

The number of PMCs available in each class and their widths need to be determined at run time by calling pmc_cpuinfo(3).

Intel Core2 PMCs are documented in Volume 3: System Programming Guide, IA-32 Intel(R) Architecture Software Developer's Manual, Order Number 253669-027US, Intel Corporation, July 2008.

These PMCs and their supported events are documented in pmc.iaf(3). Not all CPUs in this family implement fixed-function counters.

The programmable PMCs support the following capabilities:

PMC_CAP_CASCADE No
PMC_CAP_EDGE Yes
PMC_CAP_INTERRUPT Yes
PMC_CAP_INVERT Yes
PMC_CAP_READ Yes
PMC_CAP_PRECISE No
PMC_CAP_SYSTEM Yes
PMC_CAP_TAGGING No
PMC_CAP_THRESHOLD Yes
PMC_CAP_USER Yes
PMC_CAP_WRITE Yes

Event specifiers for these PMCs support the following common qualifiers:

value
Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to value.
Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true.
Invert the sense of comparison when the “cmask” qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the “cmask” qualifier.
Configure the PMC to count events happening at processor privilege level 0.
Configure the PMC to count events occurring at privilege levels 1, 2 or 3.

If neither of the “os” or “usr” qualifiers are specified, the default is to enable both.

Events that require core-specificity to be specified use a additional qualifier “core=core”, where argument core is one of:

Measure event conditions on all cores.
Measure event conditions on this core.

The default is “this”.

Events that require an agent qualifier to be specified use an additional qualifier “agent=agent”, where argument agent is one of:

Measure events associated with this bus agent.
Measure events caused by any bus agent.

The default is “this”.

Events that require a hardware prefetch qualifier to be specified use an additional qualifier “prefetch=prefetch”, where argument prefetch is one of:

Include all prefetches.
Only count hardware prefetches.
Exclude hardware prefetches.

The default is “both”.

Events that require a cache coherence qualifier to be specified use an additional qualifier “cachestate=state”, where argument state contains one or more of the following letters:

Count cache lines in the exclusive state.
Count cache lines in the invalid state.
Count cache lines in the modified state.
Count cache lines in the shared state.

The default is “eims”.

Events that require a snoop response qualifier to be specified use an additional qualifier “snoopresponse=response”, where argument response comprises of the following keywords separated by “+” signs:

Measure CLEAN responses.
Measure HIT responses.
Measure HITM responses.

The default is to measure all the above responses.

Events that require a snoop type qualifier use an additional qualifier “snooptype=type”, where argument type comprises the one of the following keywords:

Measure CMP2I snoops.
Measure CMP2S snoops.

The default is to measure both snoops.

Core2 programmable PMCs support the following events:

(Event E6H, Umask 00H) The number of times the front end is resteered.
(Event E4H, Umask 00H) The number of byte sequences mistakenly detected as taken branch instructions.
(Event 8AH, Umask 00H) The number of branch instructions that were mispredicted when decoded.
(Event 93H, Umask 00H) The number of mispredicted CALL instructions that were executed.
(Event 92H, Umask 00H) The number of CALL instructions executed.
(Event 8BH, Umask 00H) The number of conditional branches executed, but not necessarily retired.
(Event 8CH, Umask 00H) The number of mispredicted conditional branches executed.
(Event 94H, Umask 00H) The number of indirect CALL instructions executed.
(Event 8DH, Umask 00H) The number of indirect branch instructions executed.
(Event 8EH, Umask 00H) The number of mispredicted indirect branch instructions executed.
(Event E0H, Umask 00H) The number of branch instructions decoded.
(Event 88H, Umask 00H) The number of branches executed, but not necessarily retired.
(Event C4H, Umask 00H) (Alias "Branch Instruction Retired") The number of branch instructions retired. This is an architectural performance event.
(Event C5H, Umask 00H) (Alias "Branch Misses Retired") The number of mispredicted branch instructions retired. This is an architectural performance event.
(Event C4H, Umask 02H) The number of not taken branch instructions retired that were mispredicted.
(Event C4H, Umask 08H) The number taken branch instructions retired that were mispredicted.
(Event C4H, Umask 01H) The number of not taken branch instructions retired that were correctly predicted.
(Event C4H, Umask 04H) The number of taken branch instructions retired that were correctly predicted.
(Event C4H, Umask 0CH) The number of taken branch instructions retired.
(Event 89H, Umask 00H) The number of mispredicted branch instructions that were executed.
(Event 90H, Umask 00H) The number of mispredicted RET instructions executed.
(Event 91H, Umask 00H) The number of RET instructions executed that were mispredicted at decode time.
(Event 8FH, Umask 00H) The number of RET instructions executed.
(Event 97H, Umask 00H) The number of branch predicted taken with bubble 1.
(Event 98H, Umask 00H) The number of branch predicted taken with bubble 2.
[,core=core]
(Event 7DH) The number of cycles during which the core did not have any pending transactions in the bus queue.
[,agent=agent]
(Event 61H) The number of Bus Not Ready signals asserted on the bus.
[,core=core]
(Event 64H) The number of bus cycles during which the processor is receiving data.
[,agent=agent]
(Event 62H) The number of bus cycles during which the Data Ready signal is asserted on the bus.
[,agent=agent]
(Event 7AH) The number of bus cycles during which the processor drives the HIT# pin.
[,agent=agent]
(Event 7BH) The number of bus cycles during which the processor drives the HITM# pin.
[,core=core]
(Event 7FH) The number of core cycles during which I/O requests wait in the bus queue.
[,agent=agent] [,core=core]
(Event 63H) The number of bus cycles during which the LOCK signal was asserted on the bus.
[,agent=agent] [,core=core]
(Event 60H) The number of pending full cache line read transactions on the bus occurring in each cycle.
[,agent=agent] [,core=core]
(Event 6BH) The number of partial bus transactions.
[,agent=agent] [,core=core]
(Event 68H) The number of instruction fetch full cache line bus transactions.
[,agent=agent] [,core=core]
(Event 69H) The number of invalidate bus transactions.
[,agent=agent] [,core=core]
(Event 6AH) The number of partial write bus transactions.
[,agent=agent] [,core=core]
(Event 6DH) The number of deferred bus transactions.
[,agent=agent] [,core=core]
(Event 6EH) The number of burst transactions.
[,agent=agent] [,core=core]
(Event 6FH) The number of memory bus transactions.
[,agent=agent] [,core=core]
(Event 70H) The number of bus transactions of any kind.
[,agent=agent] [,core=core]
(Event 65H) The number of burst read transactions.
[,agent=agent] [,core=core]
(Event 6CH) The number of completed I/O bus transactions due to IN and OUT instructions.
[,agent=agent] [,core=core]
(Event 66H) The number of Read For Ownership bus transactions.
[,agent=agent] [,core=core]
(Event 67H) The number explicit write-back bus transactions due to dirty line evictions.
[,core=core] [,snooptype=snoop]
(Event 78H) The number of times the L1 data cache is snooped by the other core in the same processor.
(Event 3CH, Umask 01H) (Alias "Unhalted Reference Cycles") The number of bus cycles when the core is not in the halt state. This is an architectural performance event.
(Event 3CH, Umask 00H) (Alias "Unhalted Core Cycles") The number of core cycles while the core is not in a halt state. This is an architectural performance event.
(Event 3CH, Umask 02H) The number of bus cycles during which the core remains unhalted and the other core is halted.
(Event 14H, Umask 00H) The number of cycles the divider is busy. This event is only available on PMC0.
(Event C6H, Umask 01H) The number of cycles during which interrupts are disabled.
(Event C6H, Umask 02H) The number of cycles during which there were pending interrupts while interrupts were disabled.
(Event 86H, Umask 00H) The number of cycles for which an instruction fetch stalls.
(Event 19H, Umask 00H) The number of floating point operations that used data immediately after the data was generated by a non floating point execution unit.
(Event 19H, Umask 01H) The number of delayed bypass penalty cycles that a load operation incurred.
(Event 19H, Umask 02H) The number of times SIMD operations use data immediately after data, was generated by a non-SIMD execution unit.
(Event 13H, Umask 00H) The number of divide operations executed. This event is only available on PMC1.
(Event 08H, Umask 01H) The number of Data TLB misses, including misses that result from speculative accesses.
(Event 08H, Umask 04H) The number of level 0 DTLB misses due to load operations.
(Event 08H, Umask 02H) The number of Data TLB misses due to load operations.
(Event 08H, Umask 08H) The number of Data TLB misses due to store operations.
(Event 3AH, Umask 00H) The number of Enhanced Intel SpeedStep Technology transitions.
(Event ABH, Umask 02H) The number of automatic additions to the %esp register.
(Event ABH, Umask 01H) The number of times the %esp register was explicitly used in an address expression after it is implicitly used by a PUSH or POP instruction.
[,agent=agent] [,snoopresponse=response]
(Event 77H) The number of snoop responses to bus transactions.
(Event 11H, Umask 00H) The number of floating point operations executed that needed a microcode assist.
(Event 10H, Umask 00H) The number of floating point computational micro-ops executed. The event is available only on PMC0.
(Event CCH, Umask 02H) The number of transitions from MMX instructions to floating point instructions.
(Event CCH, Umask 01H) The number of transitions from floating point instructions to MMX instructions.
(Event C8H, Umask 00H) The number of hardware interrupts received.
(Event 18H, Umask 00H) The number of cycles the divider is busy and no other execution unit or load operation was in progress. This event is available only on PMC0.
(Event 87H, Umask 00H) The number of cycles the instruction length decoder stalled due to a length changing prefix.
(Event 83H, Umask 02H) The number of cycles during which the instruction queue is full.
(Event C0H, Umask 00H) (Alias "Instruction Retired") The number of instructions retired. This is an architectural performance event.
(Event C0H, Umask 01H) The number of instructions retired that contained a load operation.
(Event C0H, Umask 04H) The number of instructions retired that did not contain a load or a store operation.
(Event C0H, Umask 02H) The number of instructions retired that contained a store operation.
(Event C0H, Umask 08H) (Core2Extreme) The number of instructions retired while in VMX root operation.
(Event 82H, Umask 40H) The number of ITLB flushes.
(Event 82H, Umask 10H) The number of instruction fetches from large pages that miss the ITLB.
(Event 82H, Umask 12H) The number of instruction fetches from both large and small pages that miss the ITLB.
(Event 82H, Umask 02H) The number of instruction fetches from small pages that miss the ITLB.
(Event C9H, Umask 00H) The number of retired instructions that missed the ITLB when they were fetched.
(Event 43H, Umask 01H) The number of references to L1 data cache counting loads and stores of to all memory types.
(Event 43H, Umask 02H) The number of data reads and writes to cacheable memory.
[,cachestate=state]
(Event 42H) The number of locked reads from cacheable memory.
(Event 42H, Umask 10H) The number of cycles during which any cache line is locked by any locking instruction.
[,cachestate=state]
(Event 40H) The number of data reads from cacheable memory excluding locked reads.
[,cachestate=state]
(Event 41H) The number of data writes to cacheable memory excluding locked writes.
(Event 47H, Umask 00H) The number of modified cache lines evicted from L1 data cache.
(Event 46H, Umask 00H) The number of modified lines allocated in L1 data cache.
(Event 48H, Umask 00H) The total number of outstanding L1 data cache misses at any clock.
(Event 4EH, Umask 10H) The number of times L1 data cache requested to prefetch a data cache line.
(Event 45H, Umask 0FH) The number of lines brought into L1 data cache.
(Event 49H, Umask 01H) The number of load operations that span two cache lines.
(Event 49H, Umask 02H) The number of store operations that span two cache lines.
(Event 81H, Umask 00H) The number of instruction fetch unit misses.
(Event 80H, Umask 00H) The number of instruction fetches.
[,core=core]
(Event 21H) The number of cycles that the L2 address bus is in use.
[,core=core]
(Event 23H) The number of cycles during which the L2 data bus is busy transferring data to the core.
[,cachestate=state] [,core=core]
(Event 28H) The number of instruction cache line requests from the instruction fetch unit.
[,cachestate=state] [,core=core] [,prefetch=prefetch]
(Event 29H) The number of L2 cache read requests from L1 cache and L2 prefetchers.
[,core=core] [,prefetch=prefetch]
(Event 24H) The number of cache lines allocated in L2 cache.
[,core=core] [,prefetch=prefetch]
(Event 26H) The number of L2 cache lines evicted.
[,cachestate=state] [,core=core]
(Event 2BH) The number of locked accesses to cache lines that miss L1 data cache.
[,core=core]
(Event 25H) The number of L2 cache line modifications.
[,core=core] [,prefetch=prefetch]
(Event 27H) The number of modified lines evicted from L2 cache.
[,core=core]
(Event 32H) The number of cycles during which no L2 cache requests were pending from a core.
[,cachestate=state] [,core=core] [,prefetch=prefetch]
(Event 30H) The number of L2 cache requests that were rejected.
[,cachestate=state] [,core=core] [,prefetch=prefetch]
(Event 2EH) The number of completed L2 cache requests.
(Event 2EH, Umask 41H) (Alias "LLC Misses") The number of completed L2 cache demand requests from this core that missed the L2 cache. This is an architectural performance event.
(Event 2EH, Umask 4FH) (Alias "LLC References") The number of completed L2 cache demand requests from this core. This is an architectural performance event.
[,cachestate=state] [,core=core]
(Event 2AH) The number of store operations that miss the L1 cache and request data from the L2 cache.
(Event 03H, Umask 20H) The number of loads blocked by the L1 data cache.
(Event 03H, Umask 08H) The number of loads that partially overlap an earlier store or are aliased with a previous store.
(Event 03H, Umask 02H) The number of loads blocked by preceding stores whose address is yet to be calculated.
(Event 03H, Umask 04H) The number of loads blocked by preceding stores to the same address whose data value is not known.
(Event 03H, Umask 10H) The number of load operations that were blocked until retirement.
(Event 4CH, Umask 00H) The number of load operations that conflicted with an prefetch to the same cache line.
(Event C3H, Umask 01H) The number of times a program writes to a code section.
(Event C3H, Umask 04H) The number of times the execution pipeline was restarted due to a memory ordering conflict or memory disambiguation misprediction.
(Event AAH, Umask 08H) The number of complex instructions decoded.
(Event AAH, Umask 01H) The number of instructions decoded.
(Event 09H, Umask 01H) The number of cycles during which memory disambiguation misprediction occurs.
(Event 09H, Umask 02H) The number of load operations that were successfully disambiguated.
(Event CBH, Umask 10H) The number of retired loads that missed the DTLB.
(Event CBH, Umask 02H) The number of retired load operations that missed L1 data cache and that sent a request to L2 cache. This event is only available on PMC0.
(Event CBH, Umask 01H) The number of retired load operations that missed L1 data cache. This event is only available on PMC0.
(Event CBH, Umask 08H) The number of load operations that missed L2 cache and that caused a bus request.
(Event CBH, Umask 04H) The number of load operations that missed L2 cache.
(Event 12H, Umask 00H) The number of multiply operations executed. This event is only available on PMC1.
(Event 0CH, Umask 01H) The number of page walks executed due to an ITLB or DTLB miss.
(Event 0CH, Umask 02H) The number of cycles spent in a page walk caused by an ITLB or DTLB miss.
(Event F8H, Umask 00H) The number of downward prefetches issued from the Data Prefetch Logic unit to L2 cache.
(Event F0H, Umask 00H) The number of upward prefetches issued from the Data Prefetch Logic unit to L2 cache.
(Event D2H, Umask 0FH) The number of stall cycles due to any of RAT_STALLS.FLAGS RAT_STALLS.FPSW, RAT_STALLS.PARTIAL and RAT_STALLS.ROB_READ_PORT.
(Event D2H, Umask 04H) The number of cycles execution stalled due to a flag register induced stall.
(Event D2H, Umask 08H) The number of times the floating point status word was written.
(Event D2H, Umask 10H, Core2Extreme) The number of stalls due to other RAT resource serialization not counted by umask 0FH.
(Event D2H, Umask 02H) The number of cycles of added instruction execution latency due to the use of a register that was partially written by previous instructions.
(Event D2H, Umask 01H) The number of cycles when ROB read port stalls occurred.
(Event DCH, Umask 1FH) The number of cycles during which any resource related stall occurred.
(Event DCH, Umask 10H) The number of cycles stalled due to branch misprediction.
(Event DCH, Umask 08H) The number of cycles stalled due to writing the floating point control word.
(Event DCH, Umask 04H) The number of cycles during which the number of loads and stores in the pipeline exceeded their limits.
(Event DCH, Umask 01H) The number of cycles when the reorder buffer was full.
(Event DCH, Umask 02H) The number of cycles during which the RS was full.
(Event A0H, Umask 00H) The number of micro-ops dispatched for execution.
(Event A1H, Umask 01H) The number of cycles micro-ops were dispatched for execution on port 0.
(Event A1H, Umask 02H) The number of cycles micro-ops were dispatched for execution on port 1.
(Event A1H, Umask 04H) The number of cycles micro-ops were dispatched for execution on port 2.
(Event A1H, Umask 08H) The number of cycles micro-ops were dispatched for execution on port 3.
(Event A1H, Umask 10H) The number of cycles micro-ops were dispatched for execution on port 4.
(Event A1H, Umask 20H) The number of cycles micro-ops were dispatched for execution on port 5.
(Event 04H, Umask 01H) The number of cycles while the store buffer is draining.
(Event 06H, Umask 00H) The number of segment register loads.
(Event D5H, Umask 0FH) The number of times the any segment register was renamed.
(Event D5H, Umask 02H) The number of times the %ds register is renamed.
(Event D5H, Umask 01H) The number of times the %es register is renamed.
(Event D5H, Umask 04H) The number of times the %fs register is renamed.
(Event D5H, Umask 08H) The number of times the %gs register is renamed.
(Event D4H, Umask 0FH) The number of stalls due to lack of resource to rename any segment register.
(Event D4H, Umask 02H) The number of stalls due to lack of renaming resources for the %ds register.
(Event D4H, Umask 01H) The number of stalls due to lack of renaming resources for the %es register.
(Event D4H, Umask 04H) The number of stalls due to lack of renaming resources for the %fs register.
(Event D4H, Umask 08H) The number of stalls due to lack of renaming resources for the %gs register.
(Event CDH, Umask 00H) The number SIMD assists invoked.
(Event CAH, Umask 04H) Then number of computational SSE2 packed double precision instructions retired.
(Event CAH, Umask 01H) Then number of computational SSE2 packed single precision instructions retired.
(Event CAH, Umask 08H) Then number of computational SSE2 scalar double precision instructions retired.
(Event CAH, Umask 02H) Then number of computational SSE2 scalar single precision instructions retired.
(Event CEH, Umask 00H) The number of retired SIMD instructions that use MMX registers.
(Event C7H, Umask 1FH) The number of streaming SIMD instructions retired.
(Event C7H, Umask 04H) The number of SSE2 packed double precision instructions retired.
(Event C7H, Umask 01H) The number of SSE packed single precision instructions retired.
(Event C7H, Umask 08H) The number of SSE2 scalar double precision instructions retired.
(Event C7H, Umask 02H) The number of SSE scalar single precision instructions retired.
(Event C7H, Umask 10H) The number of SSE2 vector instructions retired.
(Event CFH, Umask 00H) The number of saturated arithmetic SIMD instructions retired.
(Event B1H, Umask 00H) The number of SIMD saturated arithmetic micro-ops executed.
(Event B0H, Umask 00H) The number of SIMD micro-ops executed.
(Event B3H, Umask 20H) The number of SIMD packed arithmetic micro-ops executed.
(Event B3H, Umask 10H) The number of SIMD packed logical micro-ops executed.
(Event B3H, Umask 01H) The number of SIMD packed multiply micro-ops executed.
(Event B3H, Umask 04H) The number of SIMD pack micro-ops executed.
(Event B3H, Umask 02H) The number of SIMD packed shift micro-ops executed.
(Event B3H, Umask 08H) The number of SIMD unpack micro-ops executed.
[,agent=agent] [,core=core]
(Event 7EH) The number of times the bus stalled for snoops.
(Event 07H, Umask 01H) The number of PREFETCHT0 instructions executed.
(Event 07H, Umask 02H) The number of PREFETCHT1 instructions executed.
(Event 07H, Umask 00H) The number of PREFETCHNTA instructions executed.
(Event 07H, Umask 03H) The number of times SSE non-temporal store instructions were executed.
(Event 4BH, Umask 01H) The number of times the PREFETCHT0 instruction executed and missed all cache levels.
(Event 4BH, Umask 02H) The number of times the PREFETCHT1 instruction executed and missed all cache levels.
(Event 4BH, Umask 00H) The number of times the PREFETCHNTA instruction executed and missed all cache levels.
(Event 04H, Umask 02H) The number of cycles while a store was waiting for another store to be globally observed.
(Event 04H, Umask 08H) The number of cycles while a store was blocked due to a conflict with an internal or external snoop.
(Event 3BH, Umask C0H) The number of thermal trips.
(Event C2H, Umask 01H) The number of micro-ops retired that fused a load with another operation.
(Event C2H, Umask 02H) The number of store address calculations that fused into one micro-op.
(Event C2H, Umask 04H) The number of times retired instruction pairs were fused into one micro-op.
(Event C2H, Umask 07H) The number of fused micro-ops retired.
(Event C2H, Umask 8H) The number of non-fused micro-ops retired.
(Event C2H, Umask 0FH) The number of micro-ops retired.
(Event C1H, Umask FEH) The number of floating point computational instructions retired.
(Event C1H, Umask 01H) The number of FXCH instructions retired.

The following table shows the mapping between the PMC-independent aliases supported by library “libpmc” and the underlying hardware events used.

pmc(3), pmc.atom(3), pmc.core(3), pmc.iaf(3), pmc.k7(3), pmc.k8(3), pmc.p4(3), pmc.p5(3), pmc.p6(3), pmc.soft(3), pmc.tsc(3), pmc_cpuinfo(3), pmclog(3), hwpmc(4)

The pmc library first appeared in FreeBSD 6.0.

The library “libpmc” library was written by Joseph Koshy <jkoshy@FreeBSD.org>.

June 8, 2009 FreeBSD-12.0