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PMC.HASWELL(3) Library Functions Manual PMC.HASWELL(3)

pmc.haswell — measurement events for Intel Haswell family CPUs

library “libpmc”

#include <pmc.h>

Intel Haswell CPUs contain PMCs conforming to version 2 of the Intel performance measurement architecture. These CPUs may contain up to two classes of PMCs:
Fixed-function counters that count only one hardware event per counter.
Programmable counters that may be configured to count one of a defined set of hardware events.

The number of PMCs available in each class and their widths need to be determined at run time by calling pmc_cpuinfo(3).

Intel Haswell PMCs are documented in Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C, Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Order Number: 325462-045US, Intel Corporation, January 2013.

These PMCs and their supported events are documented in pmc.iaf(3).

The programmable PMCs support the following capabilities:

PMC_CAP_CASCADE No
PMC_CAP_EDGE Yes
PMC_CAP_INTERRUPT Yes
PMC_CAP_INVERT Yes
PMC_CAP_READ Yes
PMC_CAP_PRECISE No
PMC_CAP_SYSTEM Yes
PMC_CAP_TAGGING No
PMC_CAP_THRESHOLD Yes
PMC_CAP_USER Yes
PMC_CAP_WRITE Yes

Event specifiers for these PMCs support the following common qualifiers:

value
Configure the Off-core Response bits.
Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches.
Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches.
Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches.
Counts the number of writeback (modified to exclusive) transactions.
Counts the number of data cacheline reads generated by L2 prefetchers.
Counts the number of RFO requests generated by L2 prefetchers.
Counts the number of code reads generated by L2 prefetchers.
L2 prefetcher to L3 for loads.
RFO requests generated by L2 prefetcher
L2 prefetcher to L3 for instruction fetches.
Bus lock and split lock requests.
Streaming store requests.
Any other request that crosses IDI, including I/O.
Catch all value for any response types.
No Supplier Information available.
M-state initial lookup stat in L3.
E-state.
S-state.
F-state.
Local DRAM Controller.
No details on snoop-related information.
No snoop was needed to satisfy the request.
A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM.
A snoop was needed and it hits in at least one snooped cache. Hit denotes a cache-line was valid before snoop effect. This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM.
A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a cache-line was in modified state before effect as a results of snoop. This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD).
Target was non-DRAM system address. This includes MMIO transactions.
value
Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to value.
Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true.
Invert the sense of comparison when the “cmask” qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the “cmask” qualifier.
Configure the PMC to count events happening at processor privilege level 0.
Configure the PMC to count events occurring at privilege levels 1, 2 or 3.

If neither of the “os” or “usr” qualifiers are specified, the default is to enable both.

Haswell programmable PMCs support the following events:

(Event 03H, Umask 02H) Loads blocked by overlapping with store buffer that cannot be forwarded.
(Event 05H, Umask 01H) Speculative cache-line split load uops dispatched to L1D.
(Event 05H, Umask 02H) Speculative cache-line split Store-address uops dispatched to L1D.
(Event 07H, Umask 01H) False dependencies in MOB due to partial compare on address.
(Event 08H, Umask 01H) Misses in all TLB levels that cause a page walk of any page size.
(Event 08H, Umask 02H) Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.
(Event 08H, Umask 02H) Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.
(Event 08H, Umask 0EH) Completed page walks in any TLB of any page size due to demand load misses
(Event 08H, Umask 10H) Cycle PMH is busy with a walk.
(Event 08H, Umask 20H) Load misses that missed DTLB but hit STLB (4K).
(Event 08H, Umask 40H) Load misses that missed DTLB but hit STLB (2M).
(Event 08H, Umask 60H) Number of cache load STLB hits. No page walk.
(Event 08H, Umask 80H) DTLB demand load misses with low part of linear-to- physical address translation missed
(Event 0DH, Umask 03H) Cycles waiting to recover after Machine Clears except JEClear. Set Cmask= 1.
(Event 0EH, Umask 01H) ncrements each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.
(Event 0EH, Umask 10H) Number of flags-merge uops allocated. Such uops adds delay.
(Event 0EH, Umask 20H) Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.
(Event 0EH, Umask 40H) Number of multiply packed/scalar single precision uops allocated.
(Event 24H, Umask 21H) Demand Data Read requests that missed L2, no rejects.
(Event 24H, Umask 41H) Demand Data Read requests that hit L2 cache.
(Event 24H, Umask E1H) Counts any demand and L1 HW prefetch data load requests to L2.
(Event 24H, Umask 42H) Counts the number of store RFO requests that hit the L2 cache.
(Event 24H, Umask 22H) Counts the number of store RFO requests that miss the L2 cache.
(Event 24H, Umask E2H) Counts all L2 store RFO requests.
(Event 24H, Umask 44H) Number of instruction fetches that hit the L2 cache.
(Event 24H, Umask 24H) Number of instruction fetches that missed the L2 cache.
(Event 24H, Umask 27H) Demand requests that miss L2 cache.
(Event 24H, Umask E7H) Demand requests to L2 cache.
(Event 24H, Umask E4H) Counts all L2 code requests.
(Event 24H, Umask 50H) Counts all L2 HW prefetcher requests that hit L2.
(Event 24H, Umask 30H) Counts all L2 HW prefetcher requests that missed L2.
(Event 24H, Umask F8H) Counts all L2 HW prefetcher requests.
(Event 24H, Umask 3FH) All requests that missed L2.
(Event 24H, Umask FFH) All requests to L2 cache.
(Event 27H, Umask 50H) Not rejected writebacks that hit L2 cache
(Event 2EH, Umask 4FH) This event counts requests originating from the core that reference a cache line in the last level cache.
(Event 2EH, Umask 41H) This event counts each cache miss condition for references to the last level cache.
(Event 3CH, Umask 00H) Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.
(Event 3CH, Umask 01H) Increments at the frequency of XCLK (100 MHz) when not halted.
(Event 48H, Umask 01H) Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1 and Edge =1 to count occurrences.
(Event 49H, Umask 01H) Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G).
(Event 49H, Umask 02H) Completed page walks due to store misses in one or more TLB levels of 4K page structure.
(Event 49H, Umask 04H) Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.
(Event 49H, Umask 0EH) Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).
(Event 49H, Umask 10H) Cycles PMH is busy with this walk.
(Event 49H, Umask 20H) Store misses that missed DTLB but hit STLB (4K).
(Event 49H, Umask 40H) Store misses that missed DTLB but hit STLB (2M).
(Event 49H, Umask 60H) Store operations that miss the first TLB level but hit the second and do not cause page walks.
(Event 49H, Umask 80H) DTLB store misses with low part of linear-to-physical address translation missed.
(Event 4CH, Umask 01H) Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.
(Event 4CH, Umask 02H) Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.
(Event 51H, Umask 01H) Counts the number of lines brought into the L1 data cache.
(Event 58H, Umask 04H) Number of integer Move Elimination candidate uops that were not eliminated.
(Event 58H, Umask 08H) Number of SIMD Move Elimination candidate uops that were not eliminated.
(Event 58H, Umask 01H) Unhalted core cycles when the thread is in ring 0.
(Event 58H, Umask 02H) Number of SIMD Move Elimination candidate uops that were eliminated.
(Event 5CH, Umask 02H) Unhalted core cycles when the thread is in ring 0.
(Event 5CH, Umask 01H) Unhalted core cycles when the thread is not in ring 0.
(Event 5EH, Umask 01H) Cycles the RS is empty for the thread.
(Event 60H, Umask 01H) Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.
(Event 60H, Umask 02H) Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.
(Event 60H, Umask 04H) Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.
(Event 60H, Umask 08H) Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.
(Event 63H, Umask 01H) Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.
(Event 63H, Umask 02H) Cycles in which the L1D is locked.
(Event 79H, Umask 02H) Counts cycles the IDQ is empty.
(Event 79H, Umask 04H) Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.
(Event 79H, Umask 08H) Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.
(Event 79H, Umask 10H) Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.
(Event 79H, Umask 20H) ncrement each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.
(Event 79H, Umask 30H) Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.
(Event 79H, Umask 18H) Counts cycles DSB is delivered at least one uops. Set Cmask = 1.
(Event 79H, Umask 18H) Counts cycles DSB is delivered four uops. Set Cmask =4.
(Event 79H, Umask 24H) Counts cycles MITE is delivered at least one uops. Set Cmask = 1.
(Event 79H, Umask 24H) Counts cycles MITE is delivered four uops. Set Cmask =4.
(Event 79H, Umask 3CH) # of uops delivered to IDQ from any path.
(Event 80H, Umask 02H) Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.
(Event 85H, Umask 01H) Misses in ITLB that causes a page walk of any page size.
(Event 85H, Umask 02H) Completed page walks due to misses in ITLB 4K page entries.
(Event 85H, Umask 04H) Completed page walks due to misses in ITLB 2M/4M page entries.
(Event 85H, Umask 0EH) Completed page walks in ITLB of any page size.
(Event 85H, Umask 10H) Cycle PMH is busy with a walk.
(Event 85H, Umask 20H) ITLB misses that hit STLB (4K).
(Event 85H, Umask 40H) ITLB misses that hit STLB (2K).
(Event 85H, Umask 60H) TLB misses that hit STLB. No page walk.
(Event 87H, Umask 01H) Stalls caused by changing prefix length of the instruction.
(Event 87H, Umask 04H) Stall cycles due to IQ is full.
(Event 88H, Umask 41H) Count conditional near branch instructions that were executed (but not necessarily retired) and not taken.
(Event 88H, Umask 81H) Count conditional near branch instructions that were executed (but not necessarily retired) and taken.
(Event 88H, Umask 82H) Count all unconditional near branch instructions excluding calls and indirect branches.
(Event 88H, Umask 84H) Count executed indirect near branch instructions that are not calls nor returns.
(Event 88H, Umask 88H) Count indirect near branches that have a return mnemonic.
(Event 88H, Umask 90H) Count unconditional near call branch instructions, excluding non call branch, executed.
(Event 88H, Umask A0H) Count indirect near calls, including both register and memory indirect, executed.
(Event 88H, Umask FFH) Counts all near executed branches (not necessarily retired).
(Event 89H, Umask 41H) Count conditional near branch instructions mispredicted as nontaken.
(Event 89H, Umask 81H) Count conditional near branch instructions mispredicted as taken.
(Event 89H, Umask 84H) Count mispredicted indirect near branch instructions that are not calls nor returns.
(Event 89H, Umask 88H) Count mispredicted indirect near branches that have a return mnemonic.
(Event 89H, Umask 90H) Count mispredicted unconditional near call branch instructions, excluding non call branch, executed.
(Event 89H, Umask A0H) Count mispredicted indirect near calls, including both register and memory indirect, executed.
(Event 89H, Umask FFH) Counts all mispredicted near executed branches (not necessarily retired).
(Event 9CH, Umask 01H) Count number of non-delivered uops to RAT per thread.
(Event A1H, Umask 01H) Cycles which a Uop is dispatched on port 0 in this thread.
(Event A1H, Umask 02H) Cycles which a Uop is dispatched on port 1 in this thread.
(Event A1H, Umask 04H) Cycles which a Uop is dispatched on port 2 in this thread.
(Event A1H, Umask 08H) Cycles which a Uop is dispatched on port 3 in this thread.
(Event A1H, Umask 10H) Cycles which a Uop is dispatched on port 4 in this thread.
(Event A1H, Umask 20H) Cycles which a Uop is dispatched on port 5 in this thread.
(Event A1H, Umask 40H) Cycles which a Uop is dispatched on port 6 in this thread.
(Event A1H, Umask 80H) Cycles which a Uop is dispatched on port 7 in this thread.
(Event A2H, Umask 01H) Cycles Allocation is stalled due to Resource Related reason.
(Event A2H, Umask 04H) Cycles stalled due to no eligible RS entry available.
(Event A2H, Umask 08H) Cycles stalled due to no store buffers available (not including draining form sync).
(Event A2H, Umask 10H) Cycles stalled due to re-order buffer full.
(Event A3H, Umask 01H) Cycles with pending L2 miss loads. Set Cmask=2 to count cycle.
(Event A3H, Umask 02H) Cycles with pending memory loads. Set Cmask=2 to count cycle.
(Event A3H, Umask 05H) Number of loads missed L2.
(Event A3H, Umask 08H) Cycles with pending L1 cache miss loads. Set Cmask=8 to count cycle.
(Event AEH, Umask 01H) Counts the number of ITLB flushes, includes 4k/2M/4M pages.
(Event B0H, Umask 01H) Demand data read requests sent to uncore.
(Event B0H, Umask 02H) Demand code read requests sent to uncore.
(Event B0H, Umask 04H) Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.
(Event B0H, Umask 08H) Data read requests sent to uncore (demand and prefetch).
(Event B1H, Umask 02H) Counts total number of uops to be executed per-core each cycle.
(Event B7H, Umask 01H) Requires MSR 01A6H
(Event BBH, Umask 01H) Requires MSR 01A7H
(Event BCH, Umask 11H) Number of DTLB page walker loads that hit in the L1+FB.
(Event BCH, Umask 21H) Number of ITLB page walker loads that hit in the L1+FB.
(Event BCH, Umask 12H) Number of DTLB page walker loads that hit in the L2.
(Event BCH, Umask 22H) Number of ITLB page walker loads that hit in the L2.
(Event BCH, Umask 14H) Number of DTLB page walker loads that hit in the L3.
(Event BCH, Umask 24H) Number of ITLB page walker loads that hit in the L3.
(Event BCH, Umask 18H) Number of DTLB page walker loads from memory.
(Event BCH, Umask 28H) Number of ITLB page walker loads from memory.
(Event BDH, Umask 01H) DTLB flush attempts of the thread-specific entries.
(Event BDH, Umask 20H) Count number of STLB flush attempts.
(Event C0H, Umask 00H) Number of instructions at retirement.
(Event C0H, Umask 01H) Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.
(Event C1H, Umask 08H) Number of transitions from AVX-256 to legacy SSE when penalty applicable.
(Event C1H, Umask 10H) Number of transitions from SSE to AVX-256 when penalty applicable.
(Event C1H, Umask 40H) Number of microcode assists invoked by HW upon uop writeback.
(Event C2H, Umask 01H) Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles.
(Event C2H, Umask 02H) Counts the number of retirement slots used each cycle.
(Event C3H, Umask 02H) Counts the number of machine clears due to memory order conflicts.
(Event C3H, Umask 04H) Number of self-modifying-code machine clears detected.
(Event C3H, Umask 20H) Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.
(Event C4H, Umask 00H) Branch instructions at retirement.
(Event C4H, Umask 01H) Counts the number of conditional branch instructions Supports PEBS retired.
(Event C4H, Umask 02H) Direct and indirect near call instructions retired.
(Event C4H, Umask 04H) Counts the number of branch instructions retired.
(Event C4H, Umask 08H) Counts the number of near return instructions retired.
(Event C4H, Umask 10H) Counts the number of not taken branch instructions retired.
It Li BR_INST_RETIRED.NEAR_TAKEN (Event C4H, Umask 20H) Number of near taken branches retired.
(Event C4H, Umask 40H) Number of far branches retired.
(Event C5H, Umask 00H) Mispredicted branch instructions at retirement
(Event C5H, Umask 01H) Mispredicted conditional branch instructions retired.
(Event C5H, Umask 04H) Mispredicted macro branch instructions retired.
(Event CAH, Umask 02H) Number of X87 FP assists due to Output values.
(Event CAH, Umask 04H) Number of X87 FP assists due to input values.
(Event CAH, Umask 08H) Number of SIMD FP assists due to Output values.
(Event CAH, Umask 10H) Number of SIMD FP assists due to input values.
(Event CAH, Umask 1EH) Cycles with any input/output SSE* or FP assists.
(Event CCH, Umask 20H) Count cases of saving new LBR records by hardware.
(Event CDH, Umask 01H) Randomly sampled loads whose latency is above a user defined threshold. A small fraction of the overall loads are sampled due to randomization.
(Event D0H, Umask 11H) Count retired load uops that missed the STLB.
(Event D0H, Umask 12H) Count retired store uops that missed the STLB.
(Event D0H, Umask 41H) Count retired load uops that were split across a cache line.
(Event D0H, Umask 42H) Count retired store uops that were split across a cache line.
(Event D0H, Umask 81H) Count all retired load uops.
(Event D0H, Umask 82H) Count all retired store uops.
(Event D1H, Umask 01H) Retired load uops with L1 cache hits as data sources.
(Event D1H, Umask 02H) Retired load uops with L2 cache hits as data sources.
(Event D1H, Umask 04H) Retired load uops with LLC cache hits as data sources.
(Event D1H, Umask 10H) Retired load uops missed L2. Unknown data source excluded.
(Event D1H, Umask 40H) Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.
(Event D2H, Umask 01H) Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.
(Event D2H, Umask 02H) Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.
(Event D2H, Umask 04H) Retired load uops which data sources were HitM responses from shared LLC.
(Event D2H, Umask 08H) Retired load uops which data sources were hits in LLC without snoops required.
(Event D3H, Umask 01H) Retired load uops which data sources missed LLC but serviced from local dram.
(Event E6H, Umask 1FH) Number of front end re-steers due to BPU misprediction.
(Event F0H, Umask 01H) Demand Data Read requests that access L2 cache.
(Event F0H, Umask 02H) RFO requests that access L2 cache.
(Event F0H, Umask 04H) L2 cache accesses when fetching instructions.
(Event F0H, Umask 08H) Any MLC or LLC HW prefetch accessing L2, including rejects.
(Event F0H, Umask 10H) L1D writebacks that access L2 cache.
(Event F0H, Umask 20H) L2 fill requests that access L2 cache.
(Event F0H, Umask 40H) L2 writebacks that access L2 cache.
(Event F0H, Umask 80H) Transactions accessing L2 pipe.
(Event F1H, Umask 01H) L2 cache lines in I state filling L2.
(Event F1H, Umask 02H) L2 cache lines in S state filling L2.
(Event F1H, Umask 04H) L2 cache lines in E state filling L2.
(Event F1H, Umask 07H) L2 cache lines filling L2.
(Event F2H, Umask 05H) Clean L2 cache lines evicted by demand.
(Event F2H, Umask 06H) Dirty L2 cache lines evicted by demand.

pmc(3), pmc.atom(3), pmc.core(3), pmc.corei7(3), pmc.corei7uc(3), pmc.haswelluc(3), pmc.iaf(3), pmc.ivybridge(3), pmc.ivybridgexeon(3), pmc.k7(3), pmc.k8(3), pmc.p4(3), pmc.p5(3), pmc.p6(3), pmc.sandybridge(3), pmc.sandybridgeuc(3), pmc.sandybridgexeon(3), pmc.soft(3), pmc.tsc(3), pmc.ucf(3), pmc.westmere(3), pmc.westmereuc(3), pmc_cpuinfo(3), pmclog(3), hwpmc(4)

The pmc library first appeared in FreeBSD 6.0.

The library “libpmc” library was written by Joseph Koshy <jkoshy@FreeBSD.org>. The support for the Haswell microarchitecture was written by Hiren Panchasara <hiren.panchasara@gmail.com>.

March 22, 2013 FreeBSD-12.0