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DESCRIPTION

The base pin number is specified in the kernel configuration file with the offset locator. The mask should have 1 or 2 bits set, indicating which pins offset from the base pin should be used (0 .. 31). Pin configurations are discussed below.

The flag locator modifies the pin configuraiton:

0x01

The PPS ASSERT signal should be triggered on the negative (falling) edge of the assert pin. The default is to trigger on the positive (rising) edge of the pin.

0x02

By default, gpiopps will use double-edge triggering when only a single pin is specified and the underlying GPIO hardware supports it. This flag disables the use of double-edge triggering.

If a single pin is specified, gpiopps uses double-edge triggering to support ASSERT and CLEAR PPS signals. If the underlying GPIO hardware does not support double-edge triggering, or if this feature is diabled in the flag locator, then only ASSERT will be signaled on the specified edge.

If two pins are specified, the first pin is used to trigger the ASSERT signal and the second pin is used to trigger the CLEAR signal. The ASSERT pin's trigger edge is specified by by the flag locator, and the CLEAR pin triggers on the opposite edge. This allows ASSERT and CLEAR signals to be triggered even if the underlying GPIO hardware does not support double-edge triggering. In this scenario, both GPIO pins would be connected in parallel to the device sending the 1PPS signals.

The offset, mask, and flag locators can also be specified when gpiopps is attached at runtime using the GPIOATTACH ioctl(2) on the gpio(4) device.